PCIe Platform Architect, US and UK

Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.

 

We are actively seeking a PCIe Platform Architect, based in either UK (Reading/Northampton) or US (Eastern or California).

 

The Role:

 

The Kandou team is looking for an outstanding engineer to architect world-leading DSP products. The ideal candidate has a strong background in application processors, systems integration, performance evaluation, and, fabrics/interconnects. Responsibilities include: Determine functional requirements based on product goals, use cases, and workload analysis.

 

Collaborate across disciplines to identify technical solutions and assess key design trade-offs. Define system/subsystem architecture for correct integration and optimized power/performance. Author product specifications and facilitate correct implementation by architecture and development teams. A successful candidate will demonstrate: Broad knowledge of computer systems and silicon architecture. Performance, power, and use case modeling expertise. Exceptional communication skills and the ability to lead cross-functional teams.

 

Influence all aspects of next generation products within Kandou’s Solution architecture team. Solution Architects guide an SoC from early concept stage through design execution and post silicon. This role involves collaboration with many teams across disciplines, platform architecture, software, firmware, packaging, and silicon validation. You will learn every part of the SoC and see your contributions in shipping products.

 

 

‪The Person:

The candidate should have strong analytical thinking and problem-solving skills with excellent attention to details. Must be organized, self-motivated and able to work effectively on teams small and large across sites. Must be able to prioritize multiple assignments and drive them to completion. Strong verbal and written communication skills are essential for driving technical conversations to successful outcomes.

 

 

‪Key Responsibilities:

 

  • Key Member of the architecture team
  • Define SoC level feature requirements, and serve as key contact point for chip capabilities
  • Invent new product features and capabilities in collaboration with architecture and design teams
  • Drive attainment on metrics such as performance, power, risk and cost over the project lifetime
  • Write SOC level architecture specifications and other documentation in a clear and concise fashion
  • ‪Collaborate with sales, marketing, architecture and design teams on roadmap features
  • Assess design bugs and recommend fixes or workarounds to balance technical requirements with schedule

 

Expected Experience:

 

  • PCIe standard expert incl. CXL protocol .
  • Preferable also an PCIe expert on electrical level
  • PCIe System knowledge incl. the different PCIe component types and how the interact with accompanying components (or something in that order)
  • TL (Transaction Layer)
  • DLL (Data Link Layer)
  • PL (Physical Layer)

 

‪Preferred Experience:

 

  • ‪Knowledge of PCIe standards and systems architecture, including experience with PCIe Gen 6/5/4/3 and USB protocols.
  • ‪Knowledge of high performance computing architecture, including experience with microprocessors, graphics processors, PC chipset hardware with general familiarity with microprocessor and PC/SoC architecture
  • ‪Additional knowledge areas include performance, power management, security, graphics, machine learning, memory systems, chip packaging, I/O technologies, SoC interconnect fabrics, power distribution, reset and clocking architecture
  • ‪Must have excellent understanding of digital/analog design concepts. Experience with multiple aspects of the ASIC design flow, is also helpful
  • ‪Knowledge of programming languages, particularly scripting languages such as Perl, Python, etc. is a plus
  • ‪Must have excellent written and verbal communications skills
  • ATS (Address Translation Services),  UIO (Unordered IO)  DOE (Data Object Exchange)

 

‪Academic Credentials:

  • ‪BS degree required; MS preferred

 

If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It!