ASIC Design Engineer

Quantenna (Nasdaq: QTNA) is a global leader and innovator of high performance Wi-Fi solutions. Founded in 2006, Quantenna has demonstrated its leadership in Wi-Fi technologies with many industry firsts into the market. Quantenna continues to innovate with the mission to perfect Wi-Fi by establishing benchmarks for speed, range, efficiency and reliability. Quantenna takes a multidimensional approach, from silicon, system to software, to assess Wi-Fi networks and provides total solutions for service providers worldwide. For more information, visit www.quantenna.com.  
 
Design and develop signal processing blocks in Verilog. The candidate must have strong knowledge of  ASIC design concept and flow. Ideal candidate must have strong background in FIR, IIR and FFT design.

Requirements

    •  Micro-architecture and RTL implementation and verification of baseband modules.
    •   Responsible for ASIC implementation of blocks which include lint, CDC, Synthesis and Timing closure.
    • Minimum BS degree in EE Engineering and 2 years of experience. Preferably an MS in Electrical Engineering with signal processing background.
    • Experience in the micro-architecture and RTL coding of signal processing blocks in communication systems.
    • Knowledge of ASIC/FPGA Design and flow.
    • Proficient in Verilog and System Verilog for RTL design or verification.
    • Good understanding on C/C++ and scripting background in Pearl/Python.
    • Excellent communication skills both written and verbal.
    • Excellent collaboration skills.
    • Debug Design, prototype and bring-up.

Responsibilities

    • Micro-architecture and RTL implementation and verification of baseband modules.
    • Responsible for ASIC implementation of blocks which include lint, CDC, Synthesis and Timing closure.
    • Debug Design, prototype and bring-up.